library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;

entity cont_ceros_significativos is
	port(
		 entrada		: IN	std_logic_vector(7 downto 0);
		 salida			: OUT	integer
		 );
end cont_ceros_significativos;

architecture arch of cont_ceros_significativos is
	signal i:integer;
begin
	process(entrada)
	begin
		bucle:
		for i in 7 downto 0 loop
			if(entrada(i) = '1') then
					salida <= 7-i;
					exit bucle;
			end if;
		end loop bucle;
	end process;
end arch;